XLOG is a typed logic programming language whose compiler and runtime run reasoning on the GPU. A single frontend parses your program, checks it, and lowers it through staged intermediate representations; a shared CUDA runtime then executes it. Four reasoning paradigms — deterministic Datalog, probabilistic inference, epistemic reasoning, and SAT/MaxSAT solving — reuse that same frontend instead of living in separate engines.

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The pipeline

Every program follows the same path. The host compiles and orchestrates; the executor dispatches CUDA kernels and manages relation state that stays resident on the device.
XLOG compilation pipeline: Source, Parser, Stratifier, Lowerer, Optimizer, and Executor run on the host; CUDA kernels and the relation store are GPU-resident.
1

Parse

A PEG grammar turns source into an abstract syntax tree. The grammar is the definitive surface of the language: if a construct does not appear in it, it does not parse.
2

Stratify

Strongly-connected-component analysis over the predicate dependency graph orders the program into strata and rejects negation or aggregation that cannot be stratified.
3

Lower

The stratified program is lowered to a relational IR (RIR) of joins, filters, projections, aggregations, and recursive fixpoints.
4

Optimize

A cost-aware pass plans join order, pushes down predicates, and promotes eligible joins to worst-case-optimal multiway joins.
5

Execute

The executor interprets the plan on the host, dispatching CUDA kernels over relations that live in device memory. Deterministic recursion runs as a semi-naive fixpoint.

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Four paradigms, one frontend

After the shared parse and stratify stages, each reasoning path branches into its own intermediate representation, built from the normalized program rather than from the deterministic RIR.
XLOG architecture: Source feeds a shared frontend that fans into Deterministic (RIR), Probabilistic (PIR to XGCF), Epistemic (EIR), and Solver (SIR) paradigms, all executing on a GPU-resident kernel provider.
ParadigmWhat it computesLearn more
Deterministic DatalogLeast-model semantics with stratified negation and aggregation, evaluated as a semi-naive fixpointLanguage reference
ProbabilisticMarginal and conditional probabilities via exact knowledge compilation or Monte Carlo samplingProbabilistic programming
EpistemicWorld-view semantics over modal know and possible operatorsEpistemic reasoning
Neural-symbolicLearned rules and neural predicates trained end-to-end with PyTorchRule learning
The intermediate representations make this concrete. Everything lowers through the relational IR (RIR); the probabilistic and solver paths compile further to a GPU-evaluable circuit format (XGCF), while the epistemic path drives GPU world-view execution directly.
XLOG IR stack: AST to RIR, which branches into PIR (provenance), EIR (epistemic), and SIR (solver); PIR and SIR compile to the XGCF circuit format and EIR drives GPU epistemic execution.

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Compile once, evaluate many

The compiled plan is structure, and structure is stable: across training iterations or repeated queries, only data and weights change, never the plan. XLOG compiles a program once and reuses the plan — and, for probabilistic inference, the compiled circuit — across evaluations. This is what makes XLOG usable inside a training loop rather than alongside it. Results stay on the GPU. Query outputs and gradient tensors are exposed through DLPack capsules and Arrow for zero-copy interop with PyTorch, JAX, and cuDF, so a downstream tensor computation reads XLOG’s output without a host round-trip.

Why GPU residency matters

The defining constraint behind XLOG’s design — and what separates it from CPU logic engines bolted onto a GPU tensor framework.